The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2018
Filed:
Apr. 14, 2017
Applicant:
Chengdu Haicun Ip Technology Llc, ChengDu, CN;
Inventor:
Guobiao Zhang, Corvallis, OR (US);
Assignees:
ChengDu HaiCun IP Technology LLC, ChengDu, SiChuan, CN;
Other;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); G11C 29/00 (2006.01); G11C 7/14 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 17/18 (2006.01);
U.S. Cl.
CPC ...
G11C 17/165 (2013.01); G11C 7/14 (2013.01); G11C 11/5692 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); G11C 29/78 (2013.01); G11C 2013/0042 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/71 (2013.01); G11C 2216/12 (2013.01);
Abstract
A multi-bit-per-cell three-dimensional read-only memory (3D-OTP) comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.