The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2018
Filed:
Aug. 02, 2017
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Masamichi Fujito, Tokyo, JP;
Hiroshi Yoshida, Tokyo, JP;
Takanori Takahashi, Tokyo, JP;
Yasuhiko Taito, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/20 (2006.01); G11C 16/34 (2006.01); G11C 16/32 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/20 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01);
Abstract
A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes '0' or '1' to both of the first memory element and the second memory element.