The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Dec. 29, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

SeoungUk Heo, Paju-si, KR;

Sahnglk Jun, Seoul, KR;

Kyeusang Yoon, Anyang-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/36 (2006.01); H01L 51/52 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3611 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2320/0219 (2013.01); G09G 2320/0223 (2013.01); H01L 27/3276 (2013.01); H01L 51/52 (2013.01);
Abstract

An array substrate of a display device includes an active area with curved corner portions and a compensation unit to reduce a difference in a parasitic capacitance of each gate line and each data line. Also, a plurality of data lines disposed to overlap the corner portions of the active area may be disposed with a different width therebetween to reduce a difference in parasitic capacitance of each gate line or data line disposed to overlap the corner portions of the active area and to reduce a resistance difference between data lines. Therefore, a degree of delay of a signal transferred through a plurality of gate lines or data lines can be similar in each gate line or data line, so that a defect can be prevented in a displayed image.


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