The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Jun. 17, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Yong-Ho Jang, Goyang-si, KR;

Woo-Seok Choi, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G02F 1/1345 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G02F 1/1345 (2013.01); G09G 3/3266 (2013.01); G09G 3/3674 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/08 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0219 (2013.01); G09G 2320/0223 (2013.01);
Abstract

Discussed are a built-in gate driver capable of improving output characteristics of the gate driver by reducing load of clock lines and a display device using the same. The built-in gate driver can include a shift register, a first clock group and a second clock group located in a non-display region of a display panel. The shift register includes a plurality of stages for individually driving gate lines of a display region. The first clock group includes clock lines arranged at a first side of the shift register. The second clock group includes clock lines arranged at a second side of the shift register. Each of the clock lines includes a main line and a branch line branched from the main line and connected to a corresponding stage. A branch line belonging to a corresponding clock group of any one of the first and second clock groups does not overlap a main line belonging to the other clock group.


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