The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10102205 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 16, 2018

Filed:

Jan. 30, 2014
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Erik Ordentlich, San Jose, CA (US);

Ron M. Roth, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/30 (2006.01); G11C 13/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 17/30 (2013.01); G06F 3/0604 (2013.01); G06F 3/0638 (2013.01); G06F 3/0679 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01);
Abstract

In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes an input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.


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