The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2018
Filed:
Dec. 27, 2015
Applicant:
Altera Corporation, San Jose, CA (US);
Inventors:
Kevin W. Mai, San Jose, CA (US);
Vishwas Tumkur Vijayendra, Santa Clara, CA (US);
Jakob Raymond Jones, San Jose, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 13/40 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4054 (2013.01); G06F 1/12 (2013.01); G06F 13/4022 (2013.01); G06F 17/505 (2013.01); G06F 17/5031 (2013.01); G06F 17/5072 (2013.01); G06F 2217/84 (2013.01);
Abstract
A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.