The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

May. 17, 2013
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

Robert W. Hormuth, Cedar Park, TX (US);

Robert L. Winter, Burnet, TX (US);

Shawn J. Dube, Austin, TX (US);

Bradley J. Booth, Austin, TX (US);

Geng Lin, Cupertino, CA (US);

Jimmy Pike, Georgetown, TX (US);

Assignee:

Dell Products, LP, Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/167 (2006.01); G06F 13/40 (2006.01); G06F 15/173 (2006.01); G06F 1/04 (2006.01); G06F 9/4401 (2018.01); H04L 12/931 (2013.01); G06F 13/28 (2006.01); G06F 21/57 (2013.01); G06F 13/00 (2006.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 1/04 (2013.01); G06F 9/4401 (2013.01); G06F 13/00 (2013.01); G06F 13/28 (2013.01); G06F 13/40 (2013.01); G06F 13/4022 (2013.01); G06F 15/17331 (2013.01); G06F 21/572 (2013.01); H04L 41/06 (2013.01); H04L 49/00 (2013.01); H04L 41/0213 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

An input/output (I/O) device includes a management controller interface, a plurality of network switching interfaces, a storage interface, a component controller interface, and a plurality of multifunction modules. The multifunction modules further include a processing node interface, a first endpoint coupled to the management controller interface, a second endpoint coupled to one of the plurality of network switching interfaces, a third endpoint coupled to a remote direct memory access (RDMA) block, a fourth endpoint coupled to the storage interface, and a fifth endpoint coupled to the component controller interface.


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