The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Apr. 11, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Guy L. Guthrie, Austin, TX (US);

Jonathan R. Jackson, Austin, TX (US);

Michael S. Siegel, Raleigh, NC (US);

William J. Starke, Round Rock, TX (US);

Jeffrey A. Stuecheli, Austin, TX (US);

Derek E. Williams, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/0815 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01); G06F 12/0831 (2016.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 12/0842 (2013.01); G06F 12/0893 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/6042 (2013.01); G06F 2212/621 (2013.01);
Abstract

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies. A first cache memory in a first vertical cache hierarchy issues on the system interconnect a request for a target cache line. Responsive to the request and prior to receiving a systemwide coherence response for the request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the request. In response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiates processing to install the target cache line in the first cache memory.


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