The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2018
Filed:
Nov. 24, 2015
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Xiao Jun Dai, Beijing, CN;
Subhendu Das, Chapel Hill, NC (US);
Zhi Gan, Beijing, CN;
Zhang Yue, Beijing, CN;
Assignee:
INTERNATIONAL BUSINESS MACHINES, Armonk, NY (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0815 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 17/30 (2006.01); G06F 12/12 (2016.01); G06F 12/0842 (2016.01); G06F 12/0891 (2016.01); G06F 12/0893 (2016.01); G06F 12/123 (2016.01); G06F 12/0846 (2016.01); G06F 12/128 (2016.01); G06F 12/14 (2006.01); G06F 12/0864 (2016.01); G06F 12/0844 (2016.01); G06F 12/122 (2016.01); G06F 12/121 (2016.01); G06F 12/127 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0842 (2013.01); G06F 12/0848 (2013.01); G06F 12/0891 (2013.01); G06F 12/0893 (2013.01); G06F 12/12 (2013.01); G06F 12/123 (2013.01); G06F 12/128 (2013.01); G06F 12/1466 (2013.01); G06F 17/30171 (2013.01); G06F 12/0844 (2013.01); G06F 12/0864 (2013.01); G06F 12/121 (2013.01); G06F 12/122 (2013.01); G06F 12/127 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/282 (2013.01); G06F 2212/283 (2013.01); G06F 2212/621 (2013.01);
Abstract
Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.