The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Jul. 29, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Rajat Mittal, San Diego, CA (US);

Hee Jun Park, San Diego, CA (US);

Young Hoon Kang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); G05D 23/19 (2006.01); G05B 13/02 (2006.01); G06F 1/20 (2006.01); H01L 23/38 (2006.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G05D 23/1917 (2013.01); G05B 13/0205 (2013.01); G06F 1/206 (2013.01); G06F 1/3206 (2013.01); H01L 23/34 (2013.01); H01L 23/38 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/072 (2013.01); H01L 2924/0002 (2013.01); Y02D 10/16 (2018.01);
Abstract

Systems, methods, and computer programs are disclosed for reducing leakage power of a system on chip (SoC). One such method comprises monitoring a plurality of temperature differentials across a respective plurality of thermoelectric coolers on a system on chip (SoC). Each of the thermoelectric coolers is dedicated to a corresponding one of a plurality of chip sections on the SoC. The thermoelectric coolers are controlled based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers.


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