The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Dec. 30, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Alex Paikin, Sunnyvale, CA (US);

Colin Johnson, San Jose, CA (US);

Tathagata Chatterjee, Allen, TX (US);

Sameer Pendharkar, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/10 (2006.01); G01R 31/26 (2014.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2628 (2013.01); G01R 31/2849 (2013.01);
Abstract

In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.


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