The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Apr. 13, 2016
Applicant:

Peernova, Inc., San Jose, CA (US);

Inventors:

Arvind Agrawal, San Jose, CA (US);

Gangesh Kumar Ganesan, Mountain View, CA (US);

Assignee:

PEERNOVA, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); H04L 9/06 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H04L 9/0643 (2013.01); H04L 9/3239 (2013.01);
Abstract

Technology, implemented in digital hardware, software, or combination thereof, for completing Secure Hash Algorithm (SHA-2) computation with generating one new hash value at each clock cycle is described. The technology includes: using synchronous logic to store the computed values every alternate clock and combinational logic to process multiple rounds of SHA in each clock; completing hash calculation in unrolled modes; using efficient adders for most 32-bit adders to improve performance.


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Agrawal, Arvind. (2018). Secure hash algorithm in digital hardware for cryptographic applications (U.S. Patent No. 10097345). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10097345

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