The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Aug. 08, 2016
Applicant:

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Sotirios Athanasiou, Grenoble, FR;

Philippe Galy, Le Touvet, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 23/528 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 21/74 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7838 (2013.01); H01L 21/743 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 27/1203 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/78615 (2013.01);
Abstract

An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.


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