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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10096582 B1

PDFFull Text
Date of Patent:
Oct. 09, 2018

Filed:

Jul. 08, 2016

Enhanced power distribution to application specific integrated circuits (asics)

Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Paul L. Mantiply, Mountain View, CA (US);

Straty Argyrakis, San Jose, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:

Edell, Shapiro & Finnan, LLC

Primary Examiner:

Timothy Thompson

Assistant Examiner:

Guillermo Egoavil

Int. Cl.
CPC ...
H05K 7/10 (2006.01); H01L 25/18 (2006.01); H02M 3/158 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H01L 25/16 (2006.01); H01L 23/538 (2006.01); H05K 1/02 (2006.01); H01L 23/367 (2006.01); H01L 25/00 (2006.01); H05K 3/34 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/3675 (2013.01); H01L 23/49827 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H02M 3/158 (2013.01); H05K 1/0204 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01); H05K 1/185 (2013.01); H05K 3/341 (2013.01); H05K 3/3436 (2013.01); H01L 24/17 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/1426 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19102 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10166 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10545 (2013.01); H05K 2201/10734 (2013.01);
Abstract

Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a substrate, an ASIC, and a voltage regulator module. The substrate includes a first side, a second side, and a vertical interconnect access (via) extending between the first side and the second side. The ASIC is mounted on the first side of the substrate in alignment with the via. The voltage regulator module is mounted on the second side of the substrate in alignment with the via so that the voltage regulator module is electrically coupled to the ASIC through the via.

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