The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Aug. 26, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Satoshi Tsukiyama, Yokohama, JP;

Hideko Mukaida, Kunitachi, JP;

Yoichiro Kurita, Minato, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H05K 1/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49827 (2013.01); H01L 23/5384 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H05K 1/00 (2013.01); H01L 23/481 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.


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