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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10096520 B1

PDFFull Text
Date of Patent:
Oct. 09, 2018

Filed:

Dec. 28, 2016

Semiconductor device and method of fabricating the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Sanghoon Baek, Seoul, KR;

Jae-Ho Park, Suwon-si, KR;

Seolun Yang, Gwacheon-si, KR;

Taejoong Song, Seongnam-si, KR;

Sang-Kyu Oh, Gwacheon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:

Volentine, Whitt & Francos, PLLC

Primary Examiner:

Sheikh Maruf

Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/02 (2006.01); H01L 21/30 (2006.01); H01L 21/8234 (2006.01); H01L 21/027 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 27/02 (2006.01); H01L 27/108 (2006.01); H01L 27/11 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/0274 (2013.01); H01L 21/3086 (2013.01); H01L 21/76224 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 27/10879 (2013.01); H01L 27/10894 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

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