The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Oct. 03, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yusuke Terada, Tokyo, JP;

Shigeya Toyokawa, Tokyo, JP;

Atsushi Maeda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/762 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1368 (2006.01); G02F 1/133 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02274 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H01L 21/31051 (2013.01); H01L 21/76224 (2013.01); H01L 21/76895 (2013.01); H01L 29/6675 (2013.01); G02F 1/1368 (2013.01); G02F 1/13306 (2013.01); G02F 2001/133302 (2013.01); G02F 2001/136295 (2013.01); H01L 27/124 (2013.01);
Abstract

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as 'a', and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as 'b', a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.


Find Patent Forward Citations

Loading…