The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Apr. 16, 2015
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Philippe Dore, Montigny-le-Bretonneux, FR;

Emmanuel Ohayon, Paris, FR;

Renaud Sirdey, Cernay-la-Ville, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/53 (2013.01); G06F 21/57 (2013.01); G06F 12/109 (2016.01); G06F 9/455 (2018.01); G06F 13/16 (2006.01); H04L 9/08 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
G06F 21/53 (2013.01); G06F 9/45558 (2013.01); G06F 12/109 (2013.01); G06F 13/16 (2013.01); G06F 21/57 (2013.01); H04L 9/0861 (2013.01); H04L 9/3247 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45587 (2013.01);
Abstract

A system for executing code with blind hypervision mechanism comprises: at least one addressable physical memory, a processor operating in at least two modes, a mode termed initialization making it possible to define at least one partition in the memory and at least one second mode termed nominal, a memory bus linking the processor to the memory, a memory partitioning unit positioned on the memory bus, the unit being adapted for restricting memory access to the partition currently executing when the processor is in a mode other than the initialization mode.


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