The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Mar. 10, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Narasimhulu Dharani Kotte, Fremont, CA (US);

Senthil Thamgaraj, Fremont, CA (US);

Robert Reed, Ei Dorado Hills, CA (US);

Hitoshi Kondo, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0873 (2016.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0873 (2013.01); G06F 11/1068 (2013.01); G06F 12/0868 (2013.01); G11C 29/52 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/214 (2013.01); G06F 2212/222 (2013.01); G06F 2212/283 (2013.01); G06F 2212/305 (2013.01); G06F 2212/313 (2013.01); G06F 2212/7206 (2013.01);
Abstract

A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.


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