The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Oct. 12, 2012
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Samuel H. Duncan, Arlington, MA (US);

Gary Ward, Santa Clara, CA (US);

M. Wasiur Rashid, San Jose, CA (US);

Lincoln G. Garlick, Santa Clara, CA (US);

Wojciech Jan Truty, Redwood City, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3887 (2013.01); G06F 9/3851 (2013.01); G06F 9/4881 (2013.01); G06F 9/5027 (2013.01); G06F 2209/5017 (2013.01);
Abstract

A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.


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