The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Aug. 23, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Naoaki Kokubun, Fujisawa Kanagawa, JP;

Hironori Uchikawa, Fujisawa Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); H03M 13/27 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
H03M 13/2906 (2013.01); G06F 11/1068 (2013.01); H03M 13/2792 (2013.01); G11C 29/52 (2013.01);
Abstract

A memory controllerof a memory systemaccording to an embodiment is provided with an encoding deviceand a memory interface. The encoding deviceis provided with an encoderwhich generates a plurality of first parities by encoding a plurality of user data by using a common code, an interleaverwhich sequentially interleaves the plurality of user data, and an XOR accumulatorwhich sequentially executes component-wise modulo-2 operation on the interleaved plurality of user data. The encodergenerates second parity by encoding a result finally obtained by executing the component-wise modulo-2 operation on a plurality of user data. The memory interfacewrites a code word sequence including the plurality of user data, the first parities and the second parity in a non-volatile memory


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