The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Apr. 09, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Ordos Yuansheng Optoelectronics Co., Ltd., Ordos, Inner Mongolia, CN;

Inventors:

Jun Wang, Beijing, CN;

Xinxin Jin, Beijing, CN;

Liang Sun, Beijing, CN;

Yuebai Han, Beijing, CN;

Guoqing Zhang, Beijing, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
H03K 17/16 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0833 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01);
Abstract

The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A−40) to (A−8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A−80) to (A−16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.


Find Patent Forward Citations

Loading…