The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Sep. 20, 2016
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

John L. Melanson, Austin, TX (US);

Eric J. King, Dripping Springs, TX (US);

Zhaohui He, Austin, TX (US);

Siddharth Maru, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/217 (2006.01); H03F 3/187 (2006.01); H04R 3/02 (2006.01);
U.S. Cl.
CPC ...
H03F 3/2173 (2013.01); H03F 3/187 (2013.01); H04R 3/02 (2013.01); H03F 2200/165 (2013.01); H03F 2200/432 (2013.01); H04R 2420/03 (2013.01);
Abstract

A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input.


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