The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Nov. 29, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Shailendra Kumar Baranwal, Richardson, TX (US);

Maurizio Granato, Milan, IT;

Giovanni Frattini, Travaco' Siccomario, IT;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/00 (2006.01); H02M 5/42 (2006.01); H02M 7/04 (2006.01); H02M 7/68 (2006.01); H02M 7/217 (2006.01); H02M 3/335 (2006.01); H02M 1/08 (2006.01);
U.S. Cl.
CPC ...
H02M 3/33515 (2013.01); H02M 1/083 (2013.01);
Abstract

An electronic device, which includes an H-bridge circuit and a miniaturized transformer that is coupled to operate at VHF frequency, and a driver circuit for an n-type power transistor of the H-bridge circuit are disclosed. The driver circuit includes a first p-type transistor and an n-type transistor coupled between an upper rail and a lower rail, with an output taken between the drains of the first p-type transistor and the n-type transistor being coupled to a gate of the n-type power transistor. The driver circuit also includes a sample-and-hold capacitor coupled to capture a drain voltage for the first n-type power transistor on a first edge of a control signal for the first n-type power transistor and a comparator coupled to compare the captured drain voltage to a lower rail on a given edge of a clock signal and to provide a comparator value. The driver circuit also includes an up/down counter, which is coupled to receive the comparator value, to adjust a counter value responsive to receiving the comparator value and to output the counter value, and a first timing circuit that is coupled to receive the counter value and to send an adjustable pulse towards a gate of the first p-type transistor and a gate of the n-type transistor.


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