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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10090393 B1

PDFFull Text
Date of Patent:
Oct. 02, 2018

Filed:

Nov. 08, 2016

Method for forming a field effect transistor device having an electrical contact

Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Steven Demuynck, Aarschot, BE;

Zheng Tao, Heverlee, BE;

Boon Teik Chan, Leuven, BE;

Liesbeth Witters, Lubbeek, BE;

Marc Schaekers, Heverlee, BE;

Antony Premkumar Peter, Heverlee, BE;

Silvia Armini, Heverlee, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:

McDonnell Boehnen Hulbert & Berghoff LLP

Primary Examiner:

Angel Roman

Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/311 (2006.01); H01L 29/45 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02115 (2013.01); H01L 21/02123 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02186 (2013.01); H01L 21/28518 (2013.01); H01L 21/28556 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76886 (2013.01); H01L 29/0847 (2013.01); H01L 29/45 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

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