The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Jun. 12, 2017
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Jozef Reinerus Maria Bergervoet, Eindhoven, NL;

Gerben Willem de Jong, Veldhoven, NL;

Gian Hoogzaad, Mook, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H01L 27/06 (2006.01); H03K 19/088 (2006.01); G11C 11/412 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0652 (2013.01); G11C 11/412 (2013.01); H03K 3/356 (2013.01); H03K 3/356104 (2013.01); H03K 19/088 (2013.01);
Abstract

A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.


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