The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Dec. 30, 2016
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Chao-Jen Wang, Hsinchu, TW;

Chih-Chia Chang, Hsinchu County, TW;

Jia-Chong Ho, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 21/027 (2006.01); H01L 21/683 (2006.01); H01L 21/3105 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 21/027 (2013.01); H01L 21/3105 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 23/367 (2013.01); H01L 23/5226 (2013.01); H01L 24/19 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/211 (2013.01);
Abstract

According to an embodiment of the present disclosure, a chip package including at least one chip, a first encapsulation layer, a redistribution layer, and a second encapsulation layer is provided. The at least one chip has an active surface, a back surface opposite to the active surface, and sidewall surfaces connecting the active surface and the back surface. The first encapsulation layer covers the sidewall surfaces. The first encapsulation layer has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the active surface and the first surface, and electrically connected to the at least one chip. The second encapsulation layer is disposed on the back surface and the second surface. A thermal expansion coefficient of the second encapsulation layer is less than a thermal expansion coefficient of the first encapsulation layer. Chip packaging methods are also provided.


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