The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Dec. 22, 2017
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventors:

Jeng-Ping Lin, Taoyuan, TW;

Chiang-Lin Shih, New Taipei, TW;

Shing-Yih Shih, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0338 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 27/10805 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01);
Abstract

The present disclosure provide a method for preparing a semiconductor structure. The semiconductor structure includes a substrate having a memory array region and a peripheral circuit region; a plurality of first line patterns positioned in the memory array region and extending along a first direction; a plurality of second line patterns positioned over the first line patterns in the memory array region; and a plurality of linear features positioned in the peripheral circuit region. The plurality of second line patterns extend along a second direction different from the first direction. The plurality of second line patterns and the plurality of linear features are positioned at substantially the same level in the substrate.


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