The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Apr. 26, 2016
Applicant:

Mstar Semiconductor, Inc., Hsinchu Hsien, TW;

Inventors:

Qi-Xin Chang, Zhubei, TW;

Chen-Nan Lin, Zhubei, TW;

Chung-Ching Chen, Zhubei, TW;

Assignee:

MSTAR SEMICONDUCTOR, INC., Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/03 (2006.01); G11C 29/38 (2006.01); G11C 29/36 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/36 (2013.01); G11C 2029/3602 (2013.01);
Abstract

A memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series.


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