The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Sep. 22, 2016
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Ahsen Jamshed Uppal, Silver Spring, MD (US);

Mitesh R. Meswani, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0647 (2013.01); G06F 3/0653 (2013.01); G06F 3/0683 (2013.01); G06F 12/08 (2013.01); G06F 2212/1016 (2013.01);
Abstract

Systems, apparatuses, and methods for implementing a memory sampling based migrating page cache are disclosed. In one embodiment, a system includes one or more processors and a multi-level memory hierarchy. The system is configured to record metadata associated with a portion of memory access instructions executed by one or more processors in one or more sampling intervals. The system generates predictions on which memory pages will be accessed in a subsequent sampling interval based on the recorded metadata. The system migrates one or more memory pages to a first memory level from a second memory level responsive to predicting that the one or more memory pages will be accessed in the subsequent sampling interval. The system also adjusts a duration of the sampling interval based on the number of memory accesses or a number of page faults per interval.


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