The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Sep. 23, 2014
Applicant:

Cornell University, Ithaca, NY (US);

Inventors:

Paula Petrica, Portland, OR (US);

Adam M. Izraelevitz, Ithaca, NY (US);

David H. Albonesi, Ithaca, NY (US);

Christine A. Shoemaker, Ithaca, NY (US);

Assignee:

Cornell University, Ithaca, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/329 (2013.01); G06F 1/3243 (2013.01); Y02D 10/152 (2018.01); Y02D 10/171 (2018.01); Y02D 10/24 (2018.01);
Abstract

The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.


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