The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Sep. 12, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventor:

Naoaki Kanagawa, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/00 (2006.01); H03K 21/00 (2006.01); H03K 21/10 (2006.01); H03K 3/356 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); G11C 16/08 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 21/10 (2013.01); G11C 16/08 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); H03K 3/356 (2013.01); H03K 19/21 (2013.01);
Abstract

According to one embodiment, a frequency divider circuit includes a 1st flip-flop including a 1st terminal to which a clock signal is input, and including a 2nd terminal to which a 1st signal is input; a 2nd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 2nd signal is input, the 2nd signal being output from the 1st flip-flop; a 3rd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 3rd signal is input, the 3rd signal being output from the 2nd flip-flop; and an exclusive OR gate including a 1st terminal to which the 4th signal is input, and including a 2nd terminal to which a 5th signal is input, the 5th signal being output from the 2nd flip-flop.


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