The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Feb. 07, 2017
Applicant:

Sandia Corporation, Albuquerque, NM (US);

Inventors:

Jason C. Neely, Albuquerque, NM (US);

Joshua Stewart, Albuquerque, NM (US);

Jarod James Delhotal, Albuquerque, NM (US);

Jack David Flicker, Albuquerque, NM (US);

Geoff L. Brennecka, Morrison, CO (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H02J 1/02 (2006.01); H01L 29/16 (2006.01); H02M 7/00 (2006.01); B60L 11/18 (2006.01); B60R 16/03 (2006.01);
U.S. Cl.
CPC ...
H02J 1/02 (2013.01); B60L 11/1803 (2013.01); H01L 29/1608 (2013.01); H02M 7/003 (2013.01); B60R 16/03 (2013.01); Y10S 903/00 (2013.01);
Abstract

A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.


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