The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Dec. 30, 2015
Applicant:

Teledyne Scientific & Imaging, Llc, Thousand Oaks, CA (US);

Inventors:

Alexandros P. Papavasiliou, Thousand Oaks, CA (US);

Jeffrey F. DeNatale, Thousand Oaks, CA (US);

David J. Gulbransen, Thousand Oaks, CA (US);

Alan Roll, Oak Park, CA (US);

Assignee:

TELEDYNE SCIENTIFIC & IMAGING, LLC, Thousand Oaks, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01); H01L 49/02 (2006.01); H01L 23/532 (2006.01); H01L 27/146 (2006.01); H01L 21/306 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 21/30604 (2013.01); H01L 21/31051 (2013.01); H01L 21/32051 (2013.01); H01L 21/32133 (2013.01); H01L 23/53228 (2013.01); H01L 27/14609 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 28/90 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01);
Abstract

An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. 'Dummy' capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.


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