The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Aug. 01, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Eduard A. Cartier, New York, NY (US);

Herbert L. Ho, New Windsor, NY (US);

Donghun Kang, Hopewell Junction, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/8242 (2006.01); H01L 29/92 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1087 (2013.01); H01L 27/1082 (2013.01); H01L 27/10832 (2013.01); H01L 27/10858 (2013.01); H01L 27/10867 (2013.01); H01L 27/10873 (2013.01); H01L 27/10882 (2013.01); H01L 28/91 (2013.01);
Abstract

A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.


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