The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Sep. 08, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventors:

Tomohiro Tamaki, Nonoichi Ishikawa, JP;

Kazutoshi Nakamura, Nonoichi Ishikawa, JP;

Ryohei Gejo, Kanazawa Ishikawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/58 (2006.01); H01L 27/06 (2006.01); H01L 29/739 (2006.01); H01L 29/861 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0664 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/7397 (2013.01); H01L 29/8613 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed. The third electrode is electrically connected to the gate electrodes.


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