The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Feb. 03, 2017
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Dong Wook Jang, Icheon-si, KR;

Kwan Su Shon, Icheon-si, KR;

Yo Han Jeong, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/50 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50008 (2013.01); H03K 19/0005 (2013.01);
Abstract

An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.


Find Patent Forward Citations

Quick Actions:

Jang, Dong. (2018). Impedance calibration circuit and semiconductor memory device including the same (U.S. Patent No. 10083763). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10083763

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