The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Jun. 14, 2016
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Min Chang Kim, Icheon-si, KR;

Chang Hyun Kim, Icheon-si, KR;

Do Yun Lee, Icheon-si, KR;

Jae Jin Lee, Icheon-si, KR;

Hun Sam Jung, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 29/26 (2006.01); G11C 29/40 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 7/10 (2013.01); G11C 7/22 (2013.01); G11C 2029/2602 (2013.01); G11C 2029/4002 (2013.01);
Abstract

A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal. The test data comparison circuit may generate a test result signal by comparing data output from the first data storage region, the second data storage region, the first data transfer circuit, and the second data transfer circuit and output the test result signal to the external equipment through the input/output pad.


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