Ring oscillator built from sram cells interconnected via standard cell-interface

Abstract

An Integrated Circuit (IC) includes a memory, circuit interconnections and control logic. The memory includes multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers, so that access to a respective SRAM cell to read and write data is through a cell-interface. The circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that includes a cascade of N stages defined by the interconnected SRAM cells. The control logic is coupled to the cell-interfaces via the circuit interconnections, and is configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator whose frequency of oscillation is indicative of a speed of the SRAM cells of the memory.