The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Jul. 10, 2017
Applicant:

Invensense, Inc., San Jose, CA (US);

Inventors:

Daesung Lee, San Jose, CA (US);

Jeff Huang, Fremont, CA (US);

Ki Young Lee, Milpitas, CA (US);

Assignee:

InvenSense, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00238 (2013.01); B81B 7/007 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2207/012 (2013.01); B81C 1/00269 (2013.01); B81C 1/00301 (2013.01); B81C 2203/0109 (2013.01); B81C 2203/035 (2013.01); B81C 2203/0792 (2013.01);
Abstract

Provided herein is a method including forming a micro-electro-mechanical system ('MEMS') wafer including a first MEMS device and a second MEMS device. A complementary metal-oxide semiconductor ('CMOS') wafer is formed including a first electrically conductive via and a second electrically conductive via. A layer stack including a first conductive layer, a second conductive layer, and a bond layer is deposited over the first electrically conductive via and the second electrically conductive via. The layer stack is etched to define a first standoff, a second standoff, a third standoff, a first bump stop over the first electrically conductive via, and a second bump stop over the second electrically conductive via. The first bump stop and the second bump stop are etched to remove the bond layer. The first bump stop is further etched to remove the second conductive layer. The MEMS wafer is bonded to the CMOS wafer.


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