The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Mar. 15, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Abdellatif Bellaouar, Richardson, TX (US);

Arul Balasubramaniyan, Plano, TX (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 17/161 (2013.01); H01L 27/0928 (2013.01); H01L 29/0649 (2013.01); H01L 29/7838 (2013.01); H03K 3/012 (2013.01);
Abstract

A method of circuit tuning, including: applying a first positive voltage and a second positive voltage to a circuit structure, the circuit structure including a p-type metal-oxide semiconductor (PMOS) device with a flipped well transistor and an n-type metal-oxide semiconductor (NMOS) device; adjusting a first threshold voltage in response to the first positive voltage being applied to a p-well region of the NMOS device and adjusting a second threshold voltage in response to the second positive voltage being applied to the p-well region of the PMOS device; and compensating the first threshold voltage and the second threshold voltage through a backgate of the PMOS device and the NMOS device relative to a same common mode voltage.


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