The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2018
Filed:
Mar. 25, 2014
Applicant:
Cypress Semiconductor Corporation, San Jose, CA (US);
Inventors:
Sagy Charel Levy, Zichron Yaakov, IL;
Frederick B. Jenne, Mountain House, CA (US);
Krishnaswamy Ramkumar, San Jose, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 21/28282 (2013.01); H01L 29/513 (2013.01); H01L 29/66833 (2013.01);
Abstract
A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.