The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Sep. 23, 2016
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Hualong Song, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 29/165 (2006.01); H01L 21/311 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/24 (2006.01); H01L 29/267 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02634 (2013.01); H01L 21/02636 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/24 (2013.01); H01L 29/267 (2013.01); H01L 29/45 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66492 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/7834 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.


Find Patent Forward Citations

Song, Hualong. (2018). Fet with local isolation layers on s/d trench sidewalls (U.S. Patent No. 10079279). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10079279

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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