The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Sep. 11, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Hiroki Okamoto, Hyogo, JP;

Hiroyuki Kutsukake, Mie, JP;

Akira Hokazono, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); G11C 13/0028 (2013.01); H01L 27/2454 (2013.01); H01L 45/1226 (2013.01); G11C 13/0007 (2013.01); G11C 2213/32 (2013.01); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01); H01L 21/02271 (2013.01); H01L 21/28158 (2013.01); H01L 21/32136 (2013.01); H01L 29/66742 (2013.01); H01L 29/78642 (2013.01); H01L 45/08 (2013.01); H01L 45/146 (2013.01); H01L 45/1608 (2013.01);
Abstract

A memory device includes a first interconnect extending in a first direction, a first and a second semiconductor members extending in a second direction, a first and a second gate lines extending in a third direction, a second and a third interconnects extending in the second direction. The first and the second semiconductor members are arranged along the first direction, with first ends in the second direction connected to the first interconnect. The second interconnect is connected to a second end in the second direction of the first semiconductor member. The third interconnect is connected to a second end in the second direction of the second semiconductor member. The distance between the first interconnect and the first gate line is longer than the distance between the first interconnect and the second gate line.


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