The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2018
Filed:
Dec. 01, 2016
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/11568 (2017.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01); H01L 29/06 (2006.01); H01L 27/11573 (2017.01); H01L 21/033 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/0332 (2013.01); H01L 21/28185 (2013.01); H01L 21/28282 (2013.01); H01L 21/84 (2013.01); H01L 27/11573 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01);
Abstract
Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.