The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

May. 26, 2015
Applicant:

Thomas P Warwick, Melbourne, FL (US);

Inventor:

Thomas P Warwick, Melbourne, FL (US);

Assignee:

R&D Circuits, Inc., South Plainfield, NJ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/552 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5225 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 23/552 (2013.01); H05K 1/0222 (2013.01); H05K 1/116 (2013.01); H01L 2224/16225 (2013.01); H05K 1/0243 (2013.01); H05K 1/113 (2013.01); H05K 2201/0723 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/09618 (2013.01); H05K 2201/09809 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/0207 (2013.01);
Abstract

Due to size and cost, it becomes advantageous for integrated circuit (IC) manufacturers to use 'single-ended' (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit board) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit board. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground. The micro-drilling methods also reduce the length of adjacent signal paths in a specific signal routing and controlled depth drilling sequence.


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