The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Mar. 28, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yong Kong Siew, Suwon-si, KR;

Sung Yup Jung, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/033 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0332 (2013.01); H01L 21/324 (2013.01); H01L 21/76801 (2013.01); H01L 21/76811 (2013.01); H01L 21/76813 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01);
Abstract

A method of forming interconnects for semiconductor devices includes forming a lower insulating layer and a lower interconnect on a semiconductor substrate, forming an insulating pattern layer on the lower interconnect through self-assembly, forming an interlayer insulating layer and a trench mask on the insulating pattern layer, forming a preparatory via hole allowing the insulating pattern layer to be exposed by removing a portion of the interlayer insulating layer, forming a trench by etching the interlayer insulating layer using the trench mask, forming a via hole allowing the lower interconnect to be exposed by selectively etching the insulating pattern layer within the preparatory via hole, and filling the trench and the via hole with an conductive material.


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