The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Apr. 30, 2015
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Daniel Sara, Sheffield, GB;

Antony John Harris, Sheffield, GB;

Håkan Lars-Göran Persson, Lund, SE;

Andrew Christopher Rose, Cambridge, GB;

Ian Bratt, San Jose, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/14 (2006.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 12/0833 (2013.01); G06F 12/1491 (2013.01); G06F 2212/1052 (2013.01);
Abstract

Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.


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