The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Nov. 05, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 1/20 (2006.01); G11C 16/10 (2006.01); G11C 5/14 (2006.01); G11C 7/04 (2006.01); G11C 7/24 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 1/20 (2013.01); G06F 3/0634 (2013.01); G06F 3/0673 (2013.01); G11C 5/143 (2013.01); G11C 7/04 (2013.01); G11C 7/24 (2013.01); G11C 16/10 (2013.01); G11C 29/027 (2013.01); G11C 29/028 (2013.01); G11C 2029/0409 (2013.01);
Abstract

A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.


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