The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Sep. 24, 2014
Applicant:

Hitachi Chemical Company, Ltd., Tokyo, JP;

Inventor:

Nobuyuki Yoshida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/42 (2006.01); H05K 3/00 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/423 (2013.01); H05K 3/0026 (2013.01); H05K 3/0035 (2013.01); H05K 3/421 (2013.01); H05K 3/4652 (2013.01); H05K 2201/0355 (2013.01); H05K 2201/09863 (2013.01); H05K 2201/2072 (2013.01); H05K 2203/1184 (2013.01); H05K 2203/1476 (2013.01); H05K 2203/1492 (2013.01);
Abstract

The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.


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